ESD (Electrostatic Discharge) protection design is a major factor in the reliability of deep-submicron CMOS Integrated Circuits (IC's). Since CMOS development technology is aggressive in the deep-submicron category, the device size and the thickness of the gate oxide are being continually reduced to improve the operating speed of the CMOS devices and integration density of the IC's. These highly scaled-down devices, however, have been found to be increasingly vulnerable to ESD. Therefore, ESD protection circuits have been added into the CMOS IC's to protect the IC's against ESD damage. Typically, ESD protection circuits are implemented around the input and output pads of the IC's to bypass ESD current away from the internal circuits of the IC's.
As a result of detailed investigations of ESD events on IC products, it is known that there are three main types of ESD events: Human-Body Model (HBM), Machine Model (MM), and Charged-Device Model (CDM). These three ESD models have been well understood, and have been widely used as the industrial ESD testing standards, as noted in the following references:
1! Standard for ESD Sensitivity Testing--Human Body Model (HBM) Component Level, EOS/ESD-S5.1, EOS/ESD Association, 1993. PA1 2! Draft Standard for ESD Sensitivity Testing--Machine Model (MM) Component Level, EOS/ESD-DS5.2, EOS/ESD Association, 1992. PA1 3! Draft Standard for Charged Device Model (CDM) ESD Sensitivity Testing (socketed CDM and non-socketed CDM), EOS/ESD-DS5.3.1, EOS/ESD Association, 1993. PA1 4! Draft Standard for Charged Device Model (CDM) ESD Sensitivity Testing (non-socketed CDM), EOS/ESD-DS5.3.2, EOS/ESD Association, 1996. PA1 5! JEDEC Field-Induced Charged Device Model (CDM) Test Method for Electrostatic Discharge (ESD) Withstand Thresholds of Microelectronics Components, JESD22-C101, May 1995. PA1 6! K. Verhaege et al., "Influence of tester, test method and device type on CDM ESD testing," Proc. of EOS/ESD Symp., 1994, pp. 49-62. PA1 7! M. Tanaka et al., "Clarification of ultra-high-speed electrostatic discharge and unification of discharge model," Proc. of EOS/ESD Symp., 1994, pp. 171-181. PA1 8! R. Renninger et al., "A field-induced charged-device model simulator," Proc. of EOS/ESD Symp., 1989, pp. 59-71. PA1 9! A. Olney, "A combined socketed and non-socketed CDM test approach for eliminating real-world CDM failures," Proc. of EOS/ESD Symp., 1996, Vol. 18, pp. 62-75. PA1 10! H. Gieser et al., "Survey on electrostatic susceptibility of integrated circuits," Proc. of European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 1994, pp. 447-456. PA1 11! C. Chen, J. Chou, W. Lur, and S. Sun, "A novel 0.25 .mu.m shallow trench isolation technology," IEEE IEDM, 1996, pp. 837-840. PA1 12! T. Maloney, "Designing MOS inputs and outputs to avoid oxide failure in the charged device model," Proc. of EOS/ESD Symp., 1988, pp. 220-227. PA1 13! Y. Fukuda, K. Kato, and E. Umemura, "ESD and latch up phenomena on advanced technology LSI," Proc. of EOS/ESD Symp., 1996, pp. 76-84. PA1 14! G. Meneghesso, J. Luchies, F. Kuper, and A. Mouthaan, "Turn-on speed of grounded gate NMOS ESD protection transistors," Proc. of European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, (Journal of Microelectronics and Reliability, Vol. 36, No. 11/12, pp. 1735-1738, 1996. PA1 15! C. Russ, K. Verhaege, K. Bock, G. Groeseneken, and H. Mass, "Simulation study for the CDM ESD behavior of the grounded-gate NMOS," Proc. of European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, (Journal of Microelectronics and Reliability, Vol. 36, No. 11/12, pp. 1739-1742, 1996. PA1 16! C. Russ, K. Verhaege, K. Bock, P. Roussel, G. Groeseneken, and H. Maes, "A compact model for the grounded-gate NMOS behavior under CDM ESD stress," Proc. of EOS/ESD Symp., 1996, pp. 302-315.
The equivalent circuits of these three ESD models are illustrated in FIG. 1. In the HBM and MM models, FIGS. 1(a) and (b), the discharge current of the ESD event is from the outside of the IC into the inside of the IC, through the input or output pins. Therefore, the ESD protection circuit is designed to limit the ESD current into the internal parts of the IC from the input or output pins.
A typical design for an ESD protection circuit 10 for HBM and MM ESD events is shown in FIG. 2, where there are primary and secondary ESD protection elements 40, 30. When an HBM or MM ESD voltage V.sub.ESD appears at the input pad 20, it acts as an input signal to the gate oxide 25 of the input stage. Since this ESD voltage V.sub.ESD may be sufficient to damage the gate oxide 25 of the input stage, it must be clamped by the ESD protection elements 40, 30. In FIG. 2, a short-channel thin-oxide NMOS is used as the secondary protection element 30 to first limit the ESD voltage V.sub.ESD across the gate oxide of the input stage. The short-channel thin-oxide NMOS 30 is designed to operate in its snapback--breakdown region, in order to clamp the voltage level across the gate oxide 25 of the input stage at as low a level as possible, when V.sub.ESD is positive.
A shorter channel length of the NMOS provides a lower snapback-breakdown voltage for clamping an ESD voltage, but is only effective at low ESD levels. Therefore, a primary ESD protection element 40, with greater ESD robustness is typically also connected to the input pad 20 to provide the main bypass for the ESD current. The devices commonly used as primary ESD protection elements are long-channel NMOS, field-oxide device (lateral bipolar transistor), or lateral SCR devices. The primary ESD protection devices with high ESD protection levels generally have a relatively high trigger (or breakdown) voltage, so that the secondary ESD protection device is activated first to clamp the ESD voltage across the gate oxide. Then, due to the increase of voltage drop across the series resistor R and the broken-down secondary ESD protection device 30, the primary ESD protection element 40 is triggered to bypass the main ESD current. Suitable designs of the ESD protection circuit of FIG. 2 can provide the input pads of IC's with high ESD robustness against HBM and MM ESD events.
In the CDM ESD model, as shown in FIG. 1(c), the ESD voltage V.sub.ESD does not come from outside the IC 15, but rather from the device itself. The substrate of the IC 15 is assumed to be charged in a CDM ESD event, and then a pin 5 of the IC 15 is shorted to ground. The charging process does not subject the IC to any ESD damage. The static charge is stored in the equivalent capacitance (Cd) of the IC 15, which is dependent on the chip size and the type of IC package. The equivalent resistance (Rd) and inductance (Ld) of the IC 15 are also dependent on the IC itself and its package. When pin 5 of the charged IC touches ground, the discharge (ESD) current goes from the charged IC 15 to ground through pin 5. This CDM ESD current is discharged from the inside of the IC 15 to the outside of the IC 15. The discharging mechanism of the CDM ESD event is, therefore, quite different from that of the HBM or MM ESD events, and results in different kinds of ESD damage to the IC.
To simulate a CDM ESD event for industrial testing, two types of CDM ESD testers have been developed. One is a socketed tester, and the other is a non-socketed tester, as described in the preceding references 3!-5!, and in the following references:
The socketed CDM ESD is discharged by a high-speed relay (switch) to ground (see reference 7!). The non-socketed CDM ESD is discharged by a grounded discharge probe (see reference 8!).
As a result of these investigations, it has been found that the CDM ESD discharge current pulse has a very fast rise time. For example, a 1000-V CDM ESD event can generate a peak discharge current of approximately 15 A, with a rise time around 0.1-0.2 ns. A typical discharge current waveform of a 1000-V CDM ESD event from a CDM ESD tester with a 4 pF verification module is shown in FIG. 3. A comparison of the discharge current waveforms between HBM (2000 V), MM (200 V), and CDM (1000 V) ESD events is shown in FIG. 4, where the CDM is clearly the fastest pulse, with a rise time of only 0.1 ns, as described in the following reference:
With such a fast CDM ESD transition, the above described known ESD protection devices can not be triggered fast enough to protect the thin gate oxide of an input stage in deep-submicron CMOS IC's. In order to provide a sufficiently fast response to a CDM ESD transition, the turn-on speed of the ESD protection device should be in the order of 10 GHz. But, in most deep-submicron CMOS technologies, it is very difficult to design and fabricate a sufficiently fast ESD protection device for commercial IC products. Moreover, in deep-submicron CMOS IC's, the gate oxide has been increasingly scaled down for high-speed and low-voltage applications. Typically, in 0.25-.mu.m CMOS technology, the gate oxide is scaled down to about 50-70 .ANG.. This type of very thin gate oxide can be ruptured by a voltage of only 6-7 V, as described in the following reference:
The very thin gate oxides of deep-submicron CMOS IC's are very sensitive to ESD stress, and traditional ESD protection devices can not turn on in time to bypass the fast discharge current generated by CDM ESD events. Therefore, CDM ESD protection design has become an urgent and challenging design problem for improving the reliability of deep-submicron CMOS IC's.
The traditional ESD protection design, as shown in FIG. 2, does not provide effective ESD protection for thin gate oxides in a CDM ESD event. This problem is illustrated in FIG. 5, where current discharge paths I.sub.ESD are shown, due to a negative CDM ESD event V.sub.ESD. As shown in FIG. 5, there are two possible ESD discharge paths, path A and path B. The negative ESD voltage V.sub.ESD is initially stored in the P-substrate of the NMOS chip 100, and the discharge current occurs when the input pad 200 is grounded. The ESD current I.sub.ESD may go through the source 300 of NMOS 100 to the VSS power line, and then along the VSS line to the ESD protection circuits 400, 500, as "path A". The short-channel NMOS 400 (secondary ESD protection element) or the ESD clamp device 500 (primary ESD protection element) may be triggered on to bypass this CDM ESD current. But, in most layouts of actual IC chips, the length of the VSS power line from the input stage 100 to the ESD protection circuits 400, 500 at the input pad 200 is long enough to cause a time delay in bypassing the fast-transition CDM ESD current, as described in the following references:
Moreover, the turn-on speed of the ESD protection devices 400, 500 is slower than the transition of the CDM ESD current. Thus, the fast CDM ESD current is first discharged through the thin gate oxide 600 of the input stage 100, as "path B", shown in FIG. 5. This causes ESD damage to the gate oxide 600 of the input stage 100, rather than being protected by the ESD protection circuits 400, 500 at the input pad 200.
To overcome this ESD damage problem for CDM ESD events, one prior art technique adds an extra short-channel NMOS device, Mn2, close to the gate oxide 600 of the input stage 100, as shown in FIG. 6. Mn2 is triggered on if there is an overstress voltage across the gate oxide 600. To provide effective protection, Mn2 has to be placed as close to gate oxide 600 as possible, in order to quickly clamp the ESD voltage across the gate oxide 600. However, since gate oxides of input stages in deep-submicron low-voltage CMOS technology have been scaled down greatly, the turn-on speed of grounded-gate NMOS Mn2 is still slower than the rise time (.about.0.1 ns) of the CDM ESD current, as noted in the following references:
Therefore, the gate oxide 600 is still vulnerable to damage from a CDM ESD event. That is, the initial discharge current, as shown in FIG. 6, still passes through gate oxide 600 when CDM ESD events occur.
Another prior art technique to protect against CDM ESD events is shown in FIG. 7, with two additional diodes Dp and Dn. However, the diode break-down speed is even slower than the turn-on speed of the short-channel NMOS device (Mn2 in FIG. 6). Therefore, diodes Dp and Dn can not provide voltage-clamping fast enough to protect the thin gate oxide 600. The fast-transition CDM ESD current will still discharge through the gate oxide 600 of input stage 100, leaving it vulnerable to damage. Thus, there is not yet an effective prior art solution to fully protect the gate oxide of an input stage in deep-submicron CMOS technology against CDM ESD events.
It is therefore an object of the present invention to overcome the disadvantages of the prior art by providing full HBM, MM, and CDM ESD protection for deep-submicron CMOS IC's.
It is another object of the present invention to provide such ESD protection with no increase in layout area.